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april 2005 1 m9999-041405 ks8721cl micrel, inc. ks8721cl 3.3v single power supply 10/100base-tx/fx mii physical layer transceiver rev. 1.2 general description the ks8721cl is a 10base-t, 100base-tx, and 100base- fx physical layer transceiver providing mii/rmii interfaces to macs and switches. using a unique mixed-signal design that extends signaling distance while reducing power consump- tion, the ks8721cl represents micrels fourth generation single-port fast ethernet phy. the ks8721cl contains 10base-t physical medium attach- ment (pma), physical medium dependent (pmd), and physi- cal coding sub-layer (pcs) functions. it also has on-chip 10base-t output filtering. this eliminates the need for external filters and allows a single set of line magnetics to be used to meet requirements for both 100base-tx and 10base-t. the ks8721cl automatically configures itself for 100mbps or 10mbps and full- or half-duplex operation, using an on-chip auto-negotiation algorithm. it is the ideal physical layer transceiver for 100base-tx/10base-t applications. features ?s ingle chip 100base-tx/100base-fx/10base-t physical layer solution ?2 .5v cmos design; 2.5/3.3v tolerance on i/o ?3 .3v single power supply with built-in voltage regulator; power consumption <340mw (including output driver current) ? fully compliant to ieee 802.3u standard ? supports mii and reduced mii (rmii) ? supports 10base-t, 100base-tx, and 100base-fx with far-end-fault (fef) detection ? supports power-down and power-saving modes ? configurable through mii serial management ports or via external control pins ? supports auto-negotiation and manual selection for 10/100mbps speed and full-/half-duplex modes ? on-chip, built-in, analog front-end filtering for both 100base-tx and 10base-t ? available in lead-free and industrial temperature packages. micrel, inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel + 1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.mic rel.com functional diagram 10/100 pulse shaper nrz/nrzi mlt3 encoder parallel/serial manchester encoder 4b/5b encoder scrambler parallel/serial transmitter tx+ tx- adaptive eq base line wander correction mlt3 decoder nrzi/nrz clock recovery 4b/5b decoder descrambler serial/parallel auto negotiation 10baset receiver manchester decoder serial/parallel pll led driver mii/rmii registers and controller interface rx- rx+ xi xo spd fdx activity link power down or saving pwrdwn rxc txd3 txd0 txd1 txd2 rxd3 txen txc txer mdc mdio col crs rxer rxd0 rxd1 rxd2 rxdv
ks8721cl micrel, inc. m9999-041405 2 april 2005 features (continued) ? led outputs for link, activity, full-/half-duplex, and speed ? supports back-to-back, fx to tx for media converter applications ? supports mdi/mdi-x auto-crossover ? commercial temperature range: 0 c to +70 c ?i ndustrial temperature range: C40 c to +85 c ? available in 48-pin lqfp ordering information part number temp. range package lead finish ks8721cl 0 c to +70 c 48-pin lqfp standard ksz8721cl 0 c to +70 c 48-pin lqfp lead-free
april 2005 3 m9999-041405 ks8721cl micrel, inc. revision history revision date summary of changes 0.90 7/20/04 created. 1.0 10/08/04 updated series resistance for crystal specification to 40 ? . 1.1 1/27/05 mdio resistor value changes to 4.7k ? . added note on strapping option pins. updated bits 1b.0 - 1b.7 to self-clearing. updated electrical characteristics. updated reference schematic for strapping option configuration to 3.3v. updated bits 1f.4-1f.2 to reserved. added aditional magnetics to qualified transformer table. added reset reference circuit. 1.2 3/16/05 added rmii timing. corrected led signal references to collision. removed ks8721cli from ordering information.
ks8721cl micrel, inc. m9999-041405 4 april 2005 t able of contents pin description ................................................................................................................ ............................................ 6 strapping option ............................................................................................................... .......................................... 9 pin configuration .............................................................................................................. ........................................ 10 introduction ................................................................................................................... ........................................ 11 100base-tx transmit ............................................................................................................ ............................ 11 100base-tx receive ............................................................................................................. ............................ 11 pll clock synthesizer .......................................................................................................... ............................... 11 scrambler/de-scrambler (100base-tx only) ....................................................................................... .............. 11 10base-t transmit .............................................................................................................. ............................... 11 10base-t receive ............................................................................................................... ............................... 11 sqe and jabber function (10base-t only) ........................................................................................ ............... 11 auto-negotia tion ............................................................................................................... ................................... 11 mii management interface ....................................................................................................... ............................ 12 mii data interface ............................................................................................................. ................................... 12 transmit clock ................................................................................................................. ............................ 12 receive clock .................................................................................................................. ............................ 12 transmit enable ................................................................................................................ ........................... 12 receive data valid ............................................................................................................. ......................... 12 error signals .................................................................................................................. .............................. 12 carrier sense .................................................................................................................. ............................. 12 collision ...................................................................................................................... .................................. 13 rmii (reduced mii) data interface .............................................................................................. ....................... 13 rmii signal definition ......................................................................................................... ................................. 13 reference clock ................................................................................................................ .................................. 13 carrier sense/receive data valid ............................................................................................... ........................ 13 receive data ................................................................................................................... .................................... 13 transmit enable ................................................................................................................ ................................... 13 transmit data .................................................................................................................. .................................... 14 collision detection ............................................................................................................ ................................... 14 rx_er .......................................................................................................................... ................................. 14 rmii ac characteristics ........................................................................................................ .............................. 14 unused rmii pins ............................................................................................................... ................................. 14 auto-crossover (auto-mdi/mdi-x) ................................................................................................ ...................... 15 power management ............................................................................................................... .............................. 16 100bt fx mode .................................................................................................................. ................................ 16 media converter operation ...................................................................................................... ........................... 16 circuit design reference for power supply ...................................................................................... .................. 17 register map ................................................................................................................... ........................................ 18 register 0h: basic control ...................................................................................................... ............................ 18 register 1h: basic status ....................................................................................................... ............................ 18 register 2h: phy identifier 1 ................................................................................................... ........................... 19 register 3h: phy identifier 2 ................................................................................................... ........................... 19 register 4h: auto-negotiation advertisement ..................................................................................... ................ 19 register 5h: auto-negotiation link partner ability .............................................................................. ................ 19 register 6h: auto-negotiation expansion ......................................................................................... .................. 20 register 7h: auto-negotiation next page ......................................................................................... .................. 20 register 8h: link partner next page ability ..................................................................................... ................... 20
april 2005 5 m9999-041405 ks8721cl micrel, inc. register map (continued) register 15h: rxer counter ...................................................................................................... ................................ 21 register 1bh: interrupt control/status register ................................................................................. ......................... 21 register 1fh: 100base-tx phy controller ......................................................................................... ....................... 21 absolute maximum ratings ....................................................................................................... ................................. 23 operating ratings .............................................................................................................. .......................................... 23 electrical characteristics ..................................................................................................... ....................................... 23 timing diagrams ................................................................................................................ .......................................... 25 selection of isolation transformer ............................................................................................. ............................... 31 selection of reference crystal ................................................................................................. .................................. 31 package information ............................................................................................................ ....................................... 32
ks8721cl micrel, inc. m9999-041405 6 april 2005 pin description pin number pin name type (1) pin function 1 mdio i/o management independent interface (mii) data i/o. this pin requires an external 4.7k pull-up resistor. 2 mdc i mii clock input. this pin is synchronous to the mdio. 3 rxd3/ ipd/o mii receive data output. rxd [3..0], these bits are synchronous with rxclk. phyad when rxdv is asserted, rxd [3..0] presents valid data to mac through the mii. rxd [3..0] is invalid when rxdv is de-asserted. during reset, the pull-up/pull-down value is latched as phyaddr [1]. see strapping options section for details. 4 rxd2/ ipd/o mii receive data output. phyad2 during reset, the pull-up/pull-down value is latched as phyaddr[2]. see strapping options section for details. 5 rxd1/ ipd/o mii receive data output. phyad3 during reset, the pull-up/pull-down value is latched as phyaddr [3]. see strapping options section for details. 6 rxd0/ ipd/o mii receive data output. phyad4 during reset, the pull-up/pull-down value is latched as phyaddr [4]. see strapping options section for details. 7 vddio p digital io 2.5 /3.3v tolerant power supply. 3.3v power input of voltage regulator. see circuit design ref. for power supply" section for details. 8 gnd gnd ground. 9r xdv/ ipd/o mii receive data valid output. crsdv/ during reset, the pull-up/pull-down value is latched as pcs_lpbk. see pcs_lpbk strapping options section for details. 10 rxc o mii receive clock output. operating at 25mhz = 100mbps, 2.5mhz = 10mbps. 11 rxer/iso ipd/o mii receive error output. during reset, the pull-up/pull-down value is latched as isolate during reset. see strapping options section for details. 12 gnd gnd ground. 13 vddc p digital core 2.5v only power supply. see circuit design ref. for power supply" section for details. 14 txer ipd mii transmit error input. 15 txc/ i/o mii transmit clock output. refclk input for crystal or an external 50mhz clock. when refclk pin is used for ref clock interface, pull up xi to vddpll 2.5v via 10k ? resistor and leave xo pin unconnected. 16 txen ipd mii transmit enable input. 17 txd0 ipd mii transmit data input. 18 txd1 ipd mii transmit data input. notes: 1. p = power supply. gnd = ground. i = input. i/o = bidirectional. ipd = input w/ internal pull-down. ipd/o = input w/ internal pull-down during reset, output pin otherwise. ipu = input w/ internal pull-up. ipu/o = input w/ internal pull-up during reset, output pin otherwise. o = output.
april 2005 7 m9999-041405 ks8721cl micrel, inc. pin number pin name type (1) pin function 19 txd2 ipd mii transmit data input. 20 txd3 ipd mii transmit data input. 21 col/rmii ipd/o mii collision detect output. during reset, the pull-up/pull-down value is latched as rmii select. see strapping options section for details. 22 crs/ ipd/o mii carrier sense output. rmii_btb during reset, the pull-up/pull-down value is latched as rmii back-to-back mode when rmii mode is selected. see strapping options section for details. 23 gnd gnd ground. 24 vddio p digital io 2.5/3.3v tolerant power supply. 3.3v power input of voltage regulator. see circuit design ref. for power supply section for details. 25 int#/ ipu/o management interface (mii) interrupt out. interrupt level set by phyad0 register 1f, bit 9. during reset, latched as phyad[0]. see strapping options section for details. 26 led0/test ipu/o link led output. the external pull-down enable test mode and only used phyad0 for the factory test. active low. link pin state led definition no link h off link l on 27 led1/ ipu/o speed led output. latched as speed (register 0, bit 13) during power-up/ spd100/ reset. see strapping options section for details. active low. nfef speed pin state led definition 10bt h off 100bt l on 28 led2/ ipu/o full-duplex led output. latched as duplex (register 0h, bit 8) during power-up/ reset. see strapping duplex options section for details. active low. duplex pin state led definition half h off full l on 29 led3/ ipu/o led output. latched as aneg_en (register 0h, bit 12) during power-up/ nwayen reset. see strapping options section for details. activity pin state led definition activity C toggle 30 pd# ipu power down. 1 = normal operation, 0 = power-down. active low. notes: 1. p = power supply. gnd = ground. i = input. i/o = bidirectional. ipd = input w/ internal pull-down. ipd/o = input w/ internal pull-down during reset, output pin otherwise. ipu = input w/ internal pull-up. ipu/o = input w/ internal pull-up during reset, output pin otherwise. o = output.
ks8721cl micrel, inc. m9999-041405 8 april 2005 pin number pin name type (1) pin function 31 vddrx p analog 2.5v power supply. see circuit design ref. for power supply section for details. 32 rx- i receive input. differential receive input pins for 100fx, 100base-tx, or 10base-t. 33 rx+ i receive input: differential receive input pin for 100fx, 100base-tx, or 10base-t. 34 fxsd/fxen ipd/o fiber mode enable / signal detect in fiber mode. if fxen = 0, fx mode is disable. the default is 0. see 100bt fx mode section for more details. 35 gnd gnd ground. 36 gnd gnd ground. 37 rext i external resistor (6.49kw ) connects to rext and gnd. 38 vddrcv p analog 2.5v power supply. 2.5v power output of voltage regulator. see circuit design ref. for power supply section for details. 39 gnd gnd ground. 40 tx- o transmit outputs: differential transmit output for 100fx, 100base-tx, or 10base-t. 41 tx+ o transmit outputs: differential transmit output for 100fx, 100base-tx, or 10base-t. 42 vddtx p transmitter 2.5v power supply. see circuit design ref. for power supply section for details. 43 gnd gnd ground. 44 gnd gnd ground. 45 xo o xtal feedback: used with xi for xtal application. 46 xi i crystal oscillator input: input for a crystal or an external 25mhz clock. if an oscillator is used, xi connects to a 3.3v tolerant oscillator, and x2 is a no- connect. 47 vddpll p analog pll 2.5v power supply. see circuit design ref. for power supply section for details. 48 rst# ipu chip reset. active low, minimum of 50 s pulse is required. notes: 1. p = power supply. gnd = ground. i = input. i/o = bidirectional. ipd = input w/ internal pull-down. ipd/o = input w/ internal pull-down during reset, output pin otherwise. ipu = input w/ internal pull-up. ipu/o = input w/ internal pull-up during reset, output pin otherwise. o = output.
april 2005 9 m9999-041405 ks8721cl micrel, inc. strapping options (1) pin number pin name type (2) description 6,5, phyad[4:1]/ ipd/o phy address latched at power-up/reset. the default phy address is 00001. 4,3 rxd[0:3] 25 phyad0/ ipu/o int# 9 (3) pcs_lpbk/ ipd/o enables pcs_lpbk mode at power-up/reset. pd (default) = disable, pu = enable. rxdv 11 (3) iso/rxer ipd/o enables isolate mode at power-up/reset. pd (default) = disable, pu = enable. 21 (3) rmii/col ipd/o enables rmii mode at power-up/reset. pd (default) = disable, pu = enable. 22 (3) rmii_btb ipd/o enable rmii back-to-back mode at power-up/reset. pd (default) = disable, crs pu = enable. 27 spd100/ ipu/o latched into register 0h bit 13 during power-up/reset. pd = 10mbps, pu (default) no fef/ = 100mbps. if spd100 is asserted during power-up/reset, this pin is also latched as led1 the speed support in register 4h. (if fxen is pulled up, the latched value 0 means no far_end _fault.) 28 duplex/ ipu/o latched into register 0h bit 8 during power-up/reset. pd = half-duplex, pu led2 (default) = full-duplex. if duplex is pulled up during reset, this pin is also latched as the duplex support in register 4h. 29 nwayen/ ipu/o nway (auto-negotiation) enable. latched into register 0h bit 12 during power-up/ led3 reset. pd = disable auto-negotiation, pu (default) = enable auto-negotiation. 30 pd# ipu power-down enable. pu (default) = normal operation, pd = power-down mode. notes: 1. strap-in is latched during power-up or reset. 2. ipu = input w/ internal pull-up. ipd/o = input w/ internal pull-down during reset, output pin otherwise. ipu/o = input w/ internal pull-up during reset, output pin otherwise. see reference circuit section for pull-up/pull-down and float information. 3. some devices may drive mii pins that are designated as output (phy) on power up, resulting in incorrect strapping values latc hed in at reset. it is recommended that an external pull-down via 1k ? resistor be used in their applications to augment the 8721's internal pull-down.
ks8721cl micrel, inc. m9999-041405 10 april 2005 pin configuration txd0 txen txc/ref_clk txer vddc txd1 txd2 txd3 mdio mdc rxd3/phyad1 rxd2/phyad2 rxd1/phyad3 rxd0/phyad4 vddio gnd 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 rxdv/pcs_lpbk rxc rxer/iso gnd 9 10 11 12 col/rmii crs/rmii_btb gnd vddio 21 22 23 24 gnd gnd fxsd/fxen rx+ rxC vddrx pd# led3/nwayen 36 35 34 33 32 31 30 29 led2/duplex led1/spd100 led0/test int#/phyad0 28 27 26 25 gnd x0 x1 vddpll rst# gnd vddtx tx+ 48 47 46 45 44 43 42 41 txC gnd vddrcv rext 40 39 38 37 48-pin lqfp (lq)
april 2005 11 m9999-041405 ks8721cl micrel, inc. introduction 100base-tx transmit the 100base-tx transmit function performs parallel-to-serial conversion, nrz-to-nrzi conversion, and mlt-3 encoding and transmission. the circuitry starts with a parallel to serial conversion that converts the 25mhz, 4-bit nibbles into a 125mhz se rial bit stream. the incoming data is clocked in at the positive edge of the txc signal. the serialized data is further converted fr om nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 6.49k ? r esistor for the 1:1 transformer ratio. its typical rise/fall time of 4ns complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output driver is also incorporated into the 100base-tx driver. 100base-tx receive the 100base-tx receive function performs adaptive equalization, dc restoration, mlt-3 to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, and serial-to-parallel conversion. the receiving side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics. it then tunes itself for optimization. this is an ongoing process and can self-adjust for environmental change s such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effects of base line wander and improve dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. finally, the nrz serial data is converted to 4-bit parallel 4b nibbles. a synchronized 25mhz rxc is generated so that the 4b nibbles are clocked out at the negative edge of rck25 and is valid for the receiver at the positive edge. when no valid data is present, the clock recovery circuit is locked to the 25mhz reference clock and both txc and rxc clocks continue to run. pll clock synthesizer the ks8721cl generates 125mhz, 25mhz, and 20mhz clocks for system timing. an internal crystal oscillator circuit provides the reference clock for the synthesizer. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic interference (emi) and baseline wander. 10base-t transmit when txen (transmit enable) goes high, data encoding and transmission begins. the ks8721cl continues to encode and transmit data as long as txen remains high. the data transmission ends when txen goes low. the last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. the output drive r is incorporated into the 100base-t driver to allow transmission with the same magnetics. they are internally wave-shaped and pre- emphasized into outputs with a typical 2.5v amplitude. the harmonic contents are at least 27db below the fundamental when driven by an all-ones, manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a pll performs the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 300mv or with short pulse widths in order to prevent noise at the rx+ or rx- input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ks8721cl decodes a data frame. this activates the carrier sense (crs) and rxdv signals and makes the receive data (rxd) available. the receive clock is maintained active during idle periods in between data reception. sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each packet is transmitted. this is required as a test of the 10base-t transmit/receive path and is called an sqe test. the 10base-t transmitter is disabled and col goes high if txen is high for more than 20ms (jabbering). if txen then goes low for more than 250ms, the 10base-t transmitter is re- enabled and col goes low. auto-negotiation the ks8721cl performs auto-negotiation by hardware strapping option (pin 29) or software (register 0.12). it automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner wheneve r
ks8721cl micrel, inc. m9999-041405 12 april 2005 auto-negotiation is enabled. it can also be configured to advertise 100base-tx or 10base-t in either full- or half-duplex mode (please refer to auto-negotiation). auto-negotiation is disabled in the fx mode. during auto-negotiation, the contents of register 4, coded in fast link pulse (flp), are sent to its link partner under the con ditions of power-on, link-loss, or restart. at the same time, the ks8721cl monitors incoming data to determine its mode of operation. the parallel detection circuit is enabled as soon as either 10base-t normal link pulse (nlp) or 100base-tx idle is detected. the operation mode is configured based on the following priority: priority 1: 100base-tx, full-duplex priority 2: 100base-tx, half-duplex priority 3: 10base-t, full-duplex priority 4: 10base-t, half-duplex when the ks8721cl receives a burst of flp from its link partner with three identical link code words (ignoring acknowledge bit), it will store these code words in register 5 and wait for the next three identical code words. once the ks8721cl detects the second code words, it then configures itself according to the above-mentioned priority. in addition, the ks8721cl also checks for 100base-tx idle or 10base-t nlp symbols. if either is detected, the ks8721cl automatically configures to match the detected operating speed. mii management interface the ks8721cl supports the ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the ks8721cl. the mdio interface consists of the following: ?a physical connection including a data line (mdio), a clock line (mdc), and an optional interrupt line (intrpt). ?a specific protocol that runs across the above-mentioned physical connection that allows one controller to communicate with multiple ks8721cl devices. each ks8721cl is assigned an mii address between 0 and 31 by the phyad inputs. ? an internal addressable set of fourteen 16-bit mdio registers. registers [0:6] are required and their functions are specified by the ieee 802.3 specifications. additional registers are provided for expanded functionality. the intprt pin functions as a management data interrupt in the mii. an active low or high in this pin indicates a status change on the ks8721cl based on 1fh.9 level control. register bits at 1bh[15:8] are the interrupt enable bits. register bits at 1bh[7: 0] are the interrupt condition bits. this interrupt is cleared by reading register 1bh. mii data interface the data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant media access controller (mac) to the ks8721cl, and for receiving data from the line. normal data transmission is implemented in 4b nibble mode (4- bit wide nibbles). transmit clock (txc): the transmit clock is normally generated by the ks8721cl from an external 25mhz reference source at the x1 input. the transmit data and control signals must always be synchronized to the txc by the mac. the ks8721cl normally samples these signals on the rising edge of the txc. receive clock (rxc): for 100base-tx links, the receive clock is continuously recovered from the line. if the link goes down, and auto-negotiation is disabled, the receive clock operates off the master input clock (x1 or txc). for 10base-t links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idl e. the ks8721cl synchronizes the receive data and control signals on the falling edge of rxc in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. transmit enable: the mac must assert txen at the same time as the first nibble of the preamble, and de-assert txen after the last bit of the packet. receive data valid: the ks8721cl asserts rxdv when it receives a valid packet. line operating speed and mii mode will determine timing changes in the following way: ? for 100base-tx links with the mii in 4b mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the data packet. ? for 10base-t links, the entire preamble is truncated. rxdv is asserted with the first nibble of the sfd 5d and remains asserted until the end of the packet. error signals: whenever the ks8721cl receives an error symbol from the network, it asserts rxer and drives 1110 (4b) on the rxd pins. when the mac asserts txer, the ks8721cl will drive h symbols (a transmit error defined in the ieee 802.3 4b/5b code group) out on the line to force signaling errors. carrier sense (crs): for 100base-tx links, a start-of-stream delimiter, or /j/k symbol pair causes assertion of carrier sense (crs). an end-of-stream delimiter, or /t/r symbol pair, causes de-assertion of crs. the pma layer will also de-assert crs if idle symbols are received without /t/r, yet in this case rxer will be asserted for one clock cycle when crs is de-
april 2005 13 m9999-041405 ks8721cl micrel, inc. asserted. for 10base-t links, crs assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (eof) marker. collision: whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the ks8721cl asserts its collision signal, which is asynchronous to any clock. rmii (reduced mii) data interface rmii interface specifies a low-pin count, reduced media independent interface (rmii) intended for use between ethernet phys and switch or repeater asics. it is fully compliant with ieee 802.3u [2]. this interface has the following characteristics: ? it is capable of supporting 10mbps and 100mbps data rates. ?a single clock reference is sourced from the mac to phy (or from an external source). ? it provides independent 2-bit wide (di-bit) transmit and receive data paths. ? it uses ttl signal levels compatible with common digital cmos asic processes. rmii signal definition direction direction signal name (w/respect to the phy) (w/respect to the mac) use ref_clk input input or output synchronous clock reference for receive, transmit and control interface crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data tx_en input output transmit enable txd[1:0] input output transmit data rx_er output input (not required) receive error reference clock (ref_clk) ref_clk is a continuous 50mhz clock that provides the timing reference for crs_dv, rxd[1:0], tx_en, txd[1:0], and rx_e. ref_clk is sourced by the mac or an external source. switch implementations may choose to provide ref_clk as an input or an output depending on whether they provide a ref_clk output or rely on an external clock distribution device. each phy device must have an input corresponding to this clock but may use a single clock input for multiple phys implemented on a single ic. carrier sense/receive data valid (crs_dv) crs_dv is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. that is, in 10base-t mode, when squelch is passed or in 100base-x mode when 2 noncontiguous zeroes in 10 bits are detected, the carrier is detected. loss-of-carrier results in the de-assertion of crs_dv synchronous to ref_clk. as carrier criteria are met, crs_dv remains continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to t he first ref_clk that follows the final di-bit. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] remains as 00 until proper receive signal decoding takes place (see definition of rxd[1:0] behavior). receive data [1:0] (rxd[1:0]) rxd[1:0] transitions synchronously to ref_clk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. in some cases (e.g., before data recovery or during error conditions), a predetermined value for rxd[1:0] is transferred instead of recovered data. rxd[1:0] remains as 00 to indicate idle when crs_dv is de- asserted. values of rxd[1:0] other than 00 when crs_dv is de-asserted are reserved for out-of-band signalling (to be defined). values other than 00 on rxd[1:0] while crs_dv is de-asserted are ignored by the mac/repeater. upon assertion of crs_dv, the phy ensures that rxd[1:0]=00 until proper receive decoding takes place. transmit enable (tx_en) transmit enable tx_en indicates that the mac is presenting di-bits on txd[1:0] on the rmii for transmission. tx_en is asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented
ks8721cl micrel, inc. m9999-041405 14 april 2005 to the rmii. tx_en is negated prior to the first ref_clk following the final di-bit of a frame. tx_en transitions synchronously with respect to ref_clk. transmit data [1:0] (txd[1:0]) transmit data txd[1:0] transitions synchronously with respect to ref_clk. when tx_en is asserted, txd[1:0] are accepted for transmission by the phy. txd[1:0] remains as 00 to indicate idle when tx_en is de-asserted. values of txd[1:0] other than 00 when tx_en is de-asserted are reserved for out-of-band signalling (to be defined). values other than 00 on txd[1:0] while tx_en is de-asserted are ignored by the phy. collision detection since the definition of crs_dv and tx_en both contain an accurate indication of the start of frame, the mac reliably regenerates the col signal of the mii by ending tx_en and crs_dv. during the ipg time following the successful transmission of a frame, the col signal is asserted by some transceivers as a self-test. the signal quality error (sqe) function is not supported by the reduced mii due to the lack of the col signal. historically, sqe was present to indicate that a transceiver located physically remote from the mac was functioning. since the reduced mii only supports chip-to-chip connections on a pcb, sqe functionality is not required. rx_er the phy provides rx_er as an output according to the rules specified in ieee 802.3u [2] (see clause 24, figure 24-11C receive state diagram). rx_er is asserted for one or more ref_clk periods to indicate that an error (e.g., a coding error or any error that a phy is capable of detecting, and that may otherwise be undetectable by the mac sublayer) is detected somewhere in the frame presently being transferred from the phy. rx_er transitions synchronously with respect to ref_clk. while crs_dv is de-asserted, rx_er has no effect on the mac. rmii ac characteristics symbol parameter min typ max unit ref_clk frequency 50 mhz ref_clk duty cycle 35 65 % t su txd[1:0], tx_en, rxd[1:0], crs_dv, rxer 4 ns t h txd[1:0], tx_en, rxd[1:0], crs_dv, rxer 2 ns data hold from ref_clk rising edge unused rmii pins input pins txd[2:3] and txer are pull-down to gnd. output pins rxd[2:3] and rxc are no connect. note that the rmii pin needs to be pulled up to enable rmii mode. rmii transmit timing ref_clk 20ns txd[1:0] txen txer t 1 t 2 parameter min typ max units ref_clk frequency 50 mhz txen, txd[1:0], tx_en, data setup to ref_clk rising edge 4 ns txen, txd[1:0], tx_en, data hold from ref_clk rising edge 2 ns
april 2005 15 m9999-041405 ks8721cl micrel, inc. rmii receive timing ref_clk 20ns t od rxd[1:0] rxdv rxer parameter min typ max units ref_clk frequency 50 mhz rxd[1:0], crs_dv, rx_er output delay from ref_clk rising edge 2.8 10 ns auto-crossover (auto-mdi/mdi-x) automatic mdi/mdi-x configuration is intended to eliminate the need for crossover cables between similar devices. the assignment of pinouts for a 10base-t/100base-tx crossover function cable is shown below. this feature eliminates the confusion in applications by allowing the use of both straight and crossover cables. this feature is controlled by register 1f:13. see the register 1fhC100base-tx phy controller section for details. receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair (rj-45) nic straight cable 10/100 ethernet m edia dependent interface 10/100 ethernet m edia dependent interface m odular connector (rj- 45) hub (r epeater or switch) m odular connector figure 1. straight through cable receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair mo dular connector (rj-45) hub (repeater or sw itch) m odular connector (rj-45) hub (r epeater or switch) cro ssover cable 10/100 ethernet me dia dependent interface 10/100 ethernet medi a dependent interface figure 2. crossover cable
ks8721cl micrel, inc. m9999-041405 16 april 2005 power management the ks8721cl offers the following modes for power management: ? power-down mode: this mode can be achieved by writing to register 0.11 or pulling pin 30 pd# low. ? power-saving mode: this mode can be disabled by writing to register 1fh.10. the ks8721cl turns off everything except for the energy detect and pll circuits when the cable is not installed. in other words, the ks8721cl shuts down most of the internal circuits to save power if there is no link. power-saving mode is in the most effective state when auto-negotiation mode is enabled. 100bt fx mode please contact your local field application engineer (fae) for a reference schematic on fiber connection. 100bt fx mode is activated when fxsd/fxen is higher than 0.6v (this pin has a default pull down). under this mode, the auto-negotiation and auto-mdi-x features are disabled. in fiber operation, the fxsd pin should connect to the signal detect (sd) output of the fiber module. the internal threshold of fxsd is around 1/2 v dd 50mv (1.25v 0.05v). above this level, the fiber signal is considered detected. the operation is summarized in the following table: fxsd/fxen condition less than 0.6v 100tx mode less than 1.25v, fx mode but greater than 0.6v no signal detected fef generated greater than 1.25 fx mode signal detected table 1. 100bt fx mode to ensure proper operation, the swing of fiber module sd should cover the threshold variation. a resistive voltage divider is recommended to adjust the sd voltage range. fef, repetition of a special pattern which consists of 84-one and 1-zero, is generated under fx mode with no signal detected. the purpose of fef is to notify the sender of a faulty link. when receiving an fef, the link will go down to indicate a fault, even with fiber signal detected. the transmitter is not affected by receiving an fef and still sends out its normal transmit pa ttern from mac. fef can be disabled by strapping pin 27 low. refer to the strapping options section. media converter operation the ks8721cl is capable of performing media conversion with two parts in a back-to-back rmii loop-back mode as indicated in the diagram. both parts are in rmii mode and with rmii btb asserted (pins 21 and 22 strapped high). one part is operating in tx mode and the other is operating in fx mode. both parts can share a common 50mhz oscillator. under this operation, auto-negotiation on the tx side prohibits 10base-t link-up. additional options can be implemented under this operation. disable the transmitter and set it at tri-state by controlling the high txd2 pin. in order to do this, rx d2 and txd2 pins need to be connected via inverter. when txd2 pin is high in both the copper and fiber operation, it is disabled transmit. meanwhile, the rxd2 pin on the copper side serves as the energy detect and can indicate if a line signal is detected. txd3 should be tied low and rxd3 allowed to float. please contact your micrel fae for a media converter reference design. figure 3. fiber module rx +/- tx +/- ftx fr x pin 34 txd (fiber mode) 21 22 pin pin 21 22 50mhz v cc osc txc/ ref_clk txc/ ref_clk rxd rxd v cc ks8721cl ks8721cl to the sd pin of the fiber module txd
april 2005 17 m9999-041405 ks8721cl micrel, inc. circuit design reference for power supply micrels integrated built-in, voltage regulator technology allows the user to save bom costs on both existing and future design s with the use of the new ks8721cl single supply, single port, 10/100 ethernet phy. 7 24 +3.3v ks8721cl 81223353 6394344 vddi/o vddi/o vddc vddpll voltage regulator 10f +2.5v +2.5vpll ferrit e bead 10f 10f 10f 13 47 +2.5va ferrit e bead vddtx out in gnd 42 31 38 10f 10 f vddrx vddrcv figure 4. circuit design the circuit design in figure 4 shows the power connections for the power supply: the 3.3v to vddi/o is the only input power source and the 2.5v at vddrcv, pin 38, is the output of the voltage regulator that needs to supply through the rest of the 2.5v vdd pins via the 2.5v power plane.
ks8721cl micrel, inc. m9999-041405 18 april 2005 address name description mode (1) default register 0h - basic control 0.15 reset 1 = software reset. bit is self-clearing. rw/sc 0 0.14 loop-back 1 = loop-back mode; 0 = normal operation. rw 0 0.13 speed select (lsb) 1 = 100mbps; 0 = 10mbps. rw set by ignored if auto-negotiation is enabled (0.12 = 1). spd100 0.12 auto-negotiation enable 1 = enable auto-negotiation process (override 0.13 and 0.8). rw set by 0 = disable auto-negotiation process. nwayen 0.11 power down 1 = power-down mode; 0 = normal operation. rw 0 0.10 isolate 1 = electrical isolation of phy from mii and tx+/tx-. rw set by iso 0 = normal operation. 0.9 restart auto-negotiation 1 = restart auto-negotiation process. rw/sc 0 0 = normal operation. bit is self-clearing. 0.8 duplex mode 1 = full-duplex; 0 = half-duplex. rw set by duplex 0.7 collision test 1 = enable col test; 0 = disable col test. rw 0 0.6:1 reserved ro 0 0.0 disable 0 = enable transmitter. r/w 0 transmitter 1 = disable transmitter. register 1h - basic status 1.15 100base-t4 1 = t4 capable; 0 = not t4 capable. ro 0 1.14 100base-tx full-duplex 1 = capable of 100base-x full-duplex. ro 1 0 = not capable of 100base-x full-duplex. 1.13 100base-tx half-duplex 1 = capable of 100base-x half-duplex. ro 1 0 = not capable of 100base-x half-duplex. 1.12 10base-t full-duplex 1 = 10mbps with full-duplex. ro 1 0 = no 10mbps with full-duplex capability. 1.11 10base-t half-duplex 1 = 10mbps with half-duplex. ro 1 0 = no 10mbps with half-duplex capability. note: 1. rw: read/write, ro: read only, sc: self clear, lh: latch high, ll: latch low. some of the default values are set by strap-in. see strapping options. register map register no. description 0h basic control register 1h basic status register 2h phy identifier i 3h phy identifier ii 4h auto-negotiation advertisement register 5h auto-negotiation link partner ability register 6h auto-negotiation expansion register 7h auto-negotiation next page register 8h link partner next page ability 15h rxer counter register 1bh interrupt control/status register 1fh 100base-tx phy control register
april 2005 19 m9999-041405 ks8721cl micrel, inc. address name description mode (1) default 1.10:7 reserved ro 0 1.6 no preamble 1 = preamble suppression; 0 = normal preamble. ro 1 1.5 auto-negotiation complete 1 = auto-negotiation process completed. ro 0 0 = auto-negotiation process not completed. 1.4 remote fault 1 = remote fault; 0 = no remote fault. ro/lh 0 1.3 auto-negotiation ability 1 = capable to perform auto-negotiation. ro 1 0 = unable to perform auto-negotiation. 1.2 link status 1 = link is up; 0 = link is down. ro/ll 0 1.1 jabber detect 1 = jabber detected; 0 = jabber not detected. default is low. ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers. ro 1 register 2h - phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally. ro 0022h unique identifier (oui). micrels oui is 0010a1 (hex). register 3h - phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally ro 000101 unique identifier (oui). micrels oui is 0010a1 (hex). 3.9:4 model number six bit manufacturers model number. ro 100001 3.3:0 revision number four bit manufacturers model number. ro 1001 register 4h - auto-negotiation advertisement 4.15 next page 1 = next page capable; 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported; 0 = no remote fault. rw 0 4.12 : 11 reserved ro 0 4.10 pause 1 = pause function supported; 0 = no pause function. rw 0 4.9 100base-t4 1 = t4 capable; 0 = no t4 capability. ro 0 4.8 100base-tx full-duplex 1 = tx with full-duplex; 0 = no tx full-duplex capability. rw set by spd100 & duplex 4.7 100base-tx 1 = tx capable; 0 = no tx capability. rw set by spd100 4.6 10base-t full-duplex 1 = 10mbps with full-duplex. rw set by 0 = no 10mbps full-duplex capability. duplex 4.5 10base-t 1 = 10mbps capable; 0 = no 10mbps capability. rw 1 4.4:0 selector field [00001] = ieee 802.3. rw 00001 register 5h - auto-negotiation link partner ability 5.15 next page 1 = next page capable; 0 = no next page capability. ro 0 5.14 acknowledge 1 = link code word received from partner. ro 0 0 = link code word not yet received. 5.13 remote fault 1 = remote fault detected; 0 = no remote fault. ro 0 5.12 reserved ro 0 note: 1. rw: read/write, ro: read only, sc: self clear, lh: latch high, ll: latch low. some of the default values are set by strap-in. see strapping options.
ks8721cl micrel, inc. m9999-041405 20 april 2005 address name description mode (1) default 5.11:10 pause 5.10 5 .11 ro 0 00 no pause 01 asymmetric pause (link partner) 10 symmetric pause 11 symmetric & asymmetric pause (local device) 5.9 100 base-t4 1 = t4 capable; 0 = no t4 capability. ro 0 5.8 100base-tx full-duplex 1 = tx with full-duplex; 0 = no tx full-duplex capability. ro 0 5.7 100base-tx 1 = tx capable; 0 = no tx capability. ro 0 5.6 10base-t full-duplex 1 = 10mbps with full-duplex. ro 0 0 = no 10mbps full-duplex capability. 5.5 10base-t 1 = 10mbps capable; 0 = no 10mbps capability. ro 0 5.4:0 selector field [00001] = ieee 802.3. ro 00001 register 6h - auto-negotiation expansion 6.15:5 reserved ro 0 6.4 parallel detection fault 1 = fault detected by parallel detection. ro/lh 0 0 = no fault detected by parallel detection. 6.3 link partner next 1 = link partner has next page capability. ro 0 page able 0 = link partner does not have next page capability. 6.2 next page able 1 = local device has next page capability. ro 1 0 = local device does not have next page capability. 6.1 page received 1 = new page received; 0 = new page not yet received. ro/lh 0 6.0 link partner 1 = link partner has auto-negotiation capability. ro 0 auto-negotiation able 0 = link partner does not have auto-negotiation capability. register 7h - auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow; 0 = last page. rw 0 7.14 reserved ro 0 7.13 message page 1 = message page; 0 = unformatted page. rw 1 7.12 acknowledge 2 1 = will comply with message. rw 0 0 = cannot comply with message. 7.11 toggle 1 = previous value of the transmitted link code word. ro 0 equaled logic one; 0 = logic zero. 7.10:0 message field 11-bit wide field to encode 2048 messages. rw 001 register 8h - link partner next page ability 8.15 next page 1 = additional next page(s) will follow; 0 = last page. ro 0 8.14 acknowledge 1 = successful receipt of link word. ro 0 0 = no successful receipt of link word. 8.13 message page 1 = message page; 0 = unformatted page. ro 0 8.12 acknowledge 2 1 = able to act on the information. ro 0 0 = not able to act on the information. 8.11 toggle 1 = previous value of transmitted link code word equal ro 0 to logic zero; 0 = previous value of transmitted link code word equal to logic one. 8.10:0 message field ro 0 note: 1. rw: read/write, ro: read only, sc: self clear, lh: latch high, ll: latch low. some of the default values are set by strap-in. see strapping options.
april 2005 21 m9999-041405 ks8721cl micrel, inc. address name description mode (1) default register 15h - rxer counter 15.15:0 rxer counter rx error counter for the rx_er in each package. ro 0000 register 1bh - interrupt control/status register 1b.15 jabber interrupt enable 1 = enable jabber interrupt; 0 = disable jabber interrupt. rw 0 1b.14 receive error 1 = enable receive error interrupt. rw 0 interrupt enable 0 = disable receive error interrupt. 1b.13 page received 1 = enable page received interrupt. rw 0 interrupt enable 0 = disable page received interrupt. 1b.12 parallel detect fault 1 = enable parallel detect fault interrupt. rw 0 interrupt enable 0 = disable parallel detect fault interrupt. 1b.11 link partner acknowledge 1 = enable link partner acknowledge interrupt. rw 0 interrupt enable 0 = disable link partner acknowledge interrupt. 1b.10 link down 1 = enable link down interrupt. rw 0 interrupt enable 0 = disable link down interrupt. 1b.9 remote fault 1 = enable remote fault interrupt. rw 0 interrupt enable 0 = disable remote fault interrupt. 1b.8 link up interrupt enable 1 = enable link up interrupt. rw 0 0 = disable link up interrupt. 1b.7 jabber interrupt 1 = jabber interrupt occurred. ro/sc 0 0 = jabber interrupt has not occurred. 1b.6 receive error interrupt 1 = receive error occurred. ro/sc 0 0 = receive error has not occurred. 1b.5 page receive interrupt 1 = page receive occurred. ro/sc 0 0 = page receive has not occurred. 1b.4 parallel detect 1 = parallel detect fault occurred. ro/sc 0 fault interrupt 0 = parallel detect fault has not occurred. 1b.3 link partner 1 = link partner acknowledge occurred. ro/sc 0 acknowledge interrupt 0 = link partner acknowledge has not occurred. 1b.2 link down interrupt 1 = link down occurred. ro/sc 0 0 = link down has not occurred. 1b.1 remote fault interrupt 1 = remote fault occurred. ro/sc 0 0 = remote fault has not occurred. 1b.0 link up interrupt 1 = link up interrupt occurred. ro/sc 0 0 = link up interrupt has not occurred. register 1fh - 100base-tx phy controller 1f.15:14 reserved 1f:13 pairswap disable 1 = disable mdi/mdi-x; 0 = enable mdi/mdi-x. r/w 0 1f.12 energy detect 1 = presence of signal on rx+/rx- analog wire pair. ro 0 0 = no signal detected on rx+/rx-. 1f.11 force link 1 = force link pass; 0 = normal link operation. r/w 0 this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. 1f.10 power-saving 1 = enable power-saving; 0 = disable. rw 1 1f.9 interrupt level 1 = interrupt pin active high; 0 = active low. rw 0 1f.8 enable jabber 1 = enable jabber counter; 0 = disable. rw 1 1f.7 auto-negotiation complete 1 = auto-negotiation complete; 0 = not complete. rw 0 note: 1. rw: read/write, ro: read only, sc: self clear, lh: latch high, ll: latch low. some of the default values are set by strap-in. see strapping options.
ks8721cl micrel, inc. m9999-041405 22 april 2005 address name description mode (1) default 1f.6 enable pause 1 = flow control capable; 0 = no flow control. ro 0 (flow-control result) 1f.5 phy isolate 1 = phy in isolate mode; 0 = not isolated. ro 0 1f.4:2 reserved 1f.1 enable sqe test 1 = enable sqe test; 0 = disable. rw 0 1f.0 disable data scrambling 1 = disable scrambler; 0 = enable. rw 0 note: 1. rw: read/write, ro: read only, sc: self clear, lh: latch high, ll: latch low. some of the default values are set by strap-in. see strapping options.
april 2005 23 m9999-041405 ks8721cl micrel, inc. electrical characteristics (4) v dd = 3.3v 10% symbol parameter test condition min typ max units total supply current (including tx output driver current) (5) i dd1 normal 100base-tx including 43ma output current 116 ma i dd2 normal 10base-t (independent of including 103ma output current 151 ma utilization) i dd3 power-saving mode 1 auto-negotiation is enable 47 ma i dd5 power-down mode 4ma ttl inputs v ih input high voltage 1/2v dd (i/o) v +0.2 v il input low voltage 0.8 v i in input current v in = gnd ~ v dd C10 10 a ttl outputs v oh output high voltage i oh = C4ma 1/2v dd (i/o) v +0.6 v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri-state leakage 10 a 100base-tx receive r in rx+/rxC differential input 8 k ? resistance propagation delay from magnetics to rdtx 50 110 ns 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 50 ? from each output to v dd 0.95 1.05 v v imb output voltage imbalance 50 ? from each output to v dd 2% t r , t t rise/fall time 35ns rise/fall time imbalance 0 0.5 ns notes: 1. exceeding the absolute maximum rating(s) may cause permanent damage to the device. operating at maximum conditions for extend ed periods may affect device reliability. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate lo gic voltage level (ground to v dd ). 3. no hs (heat spreader) in package. 4. specification for packaged product only. 5. there is 100% data transmission in full-duplex mode and a minimum ipg with a 130-meter cable. absolute maximum ratings (1) storage temperature (t s ) ....................... C55 c to +150 c supply referenced to gnd ........................ C0.5v to +4.0v all pins ........................................................ C0.5v to +4.0v important: please read the notes at the bottom of the page. operating ratings (2) supply voltage (v dd_pll , v dd_tx , v dd_rxc , v dd_rcv, v ddc ) ........ +2.5v (v ddio ) ................................................................... +3.3v ambient temperature (t a ) commercial ................................................ 0 c to +70 c industrial ................................................. C40 c to +85 c package thermal resistance (3) lqfp ( ja ) no airflow ................................................... 83.56 c/w
ks8721cl micrel, inc. m9999-041405 24 april 2005 symbol parameter condition min typ max units 100base-tx transmit (measured differentially after 1:1 transformer) duty cycle distortion 0.5 ns overshoot 5% v set reference voltage of iset 0.75 v propagation delay from tdtx to magentics 45 60 ns jitters 0.7 1.4 ns (pp) 10base-tx receive r in rx+/rxC differential 8kw input resistance v sq squelch threshold 5mhz square wave 400 mv 10base-tx transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 50w from each output to v dd 2.2 2.8 v jitters added 50w from each output to v dd 3.5 ns t r , t t rise/fall time 25 ns clock outputs x1, x2 crystal oscillator 25 mhz rxc 100 receive clock, 100tx 25 mhz rxc 10 receive clock, 10t 2.5 mhz receive clock jitters 3.0 ns (pp) txc 100 transmit clock, 100tx 25 mhz txc 10 transmit clock, 10t 2.5 mhz transmit clock jitters 1.8 ns (pp)
april 2005 25 m9999-041405 ks8721cl micrel, inc. ti ming diagrams t x c t h d 2 t s u 2 t x e n t x d [ 3 :0 ] t s u 1 t h d 1 c r s t c r s 2 t c r s 1 t x p / t xm t l a t v a l i d d a t a t x c t s q e c o l t s q e p sq e t i m i n g t x e n figure 5. 10base-t mii transmit timing symbol parameter min typ max units t su1 txd [3:0] set-up to txc high 10 ns t su2 txen set-up to txc high 10 ns t hd1 txd [3:0] hold after txc high 0 ns t hd2 txen hold after txc high 0 ns t crs1 txen high to crs asserted latency 4 bt (1) t crs2 txen low to crs de-asserted latency 8 bt t lat txen high to txp/txm output (tx latency) 4 bt t sqe col (sqe) delay after txen de-asserted 2.5 s t sqep col (sqe) pulse duration 1.0 s table 2. 10base-t mii transmit timing parameters note: 1. bt = bit time. 1bt = 10ns @ 100bt.
ks8721cl micrel, inc. m9999-041405 26 april 2005 txc t su2 txen t hd2 txd[ 3:0], txer t su1 crs t crs2 t c rs1 tx+/tx- t lat t hd1 symbol out data in figure 6. 100base-t mii transmit timing symbol parameter min typ max units t su1 txd [3:0] set-up to txc high 10 ns t su2 txen set-up to txc high 10 ns t hd1 txd [3:0] hold after txc high 0 ns t hd2 txer hold after txc high 0 ns t hd3 txen hold after txc high 0 ns t crs1 txen high to crs asserted latency 4 bt t crs2 txen low to crs de-asserted latency 4 bt t lat txen high to tx+/txC output (tx latency) 9 bt table 3. 100base-t mii transmit timing parameters
april 2005 27 m9999-041405 ks8721cl micrel, inc. rx+/rx- rxd[ 3:0] rxer crs t crs1 t crs2 rxdv t rlat t su t hd rxc t wl t wh t p end of stream start of stream figure 7. 100base-t mii receive timing symbol parameter min typ max units t p rxc period 40 ns t wl rxc pulse width 20 ns t wh rxc pulse width 20 ns t su rxd [3:0], rxer, rxdv set-up to rising edge of rxc 20 ns t hd rxd [3:0], rxer, rxdv hold from rising edge of rxc 20 ns t rlat crs to rxd latency, 4b or 5b aligned 6 bt t crs1 start of stream to csr asserted 106 138 ns t crs2 end of stream to csr de-asserted 154 186 ns table 4. 100base-t mii receive timing parameters
ks8721cl micrel, inc. m9999-041405 28 april 2005 tx+/tx- clock pulse data pulse clock pulse t btb tx+/tx- data pulse flp burst flp burst t flpw t ctd t ctc t pw t pw figure 8. auto-negotiation/fast link pulse timing symbol parameter min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 69 s t ctc clock pulse to clock pulse 136 s number of clock/data pulses per burst 17 33 s table 5. auto-negotiation/fast link pulse timing
april 2005 29 m9999-041405 ks8721cl micrel, inc. t md1 valid data mdi o (into chip) valid data mdc t md2 mdi o (out of chip) valid data t md3 t p figure 9. serial management interface timing symbol parameter min typ max units t p mdc period 400 ns t md1 mdio set-up to mdc (mdio as input) 10 ns t md2 mdio hold after mdc (mdio as input) 10 ns t md3 mdc to mdio valid (mdio as output) 222 ns table 6. serial management interface timing
ks8721cl micrel, inc. m9999-041405 30 april 2005 tsr s upply volt age rst_n str ap-in value figure 10. reset timing symbol parameter min typ max units t sr stable supply voltages to reset high 50 s table 7. reset timing parameters reset circuit diagram micrel recommendeds the following discrete reset circuit as shown in figure 11 when powering up the ks8721cl device. for the application where the reset circuit signal comes from another device (e.g., cpu, fpga, etc), we recommend the reset circuit as shown in figure 12. vcc r 10k d2 c 10f d1 cpu/fpga rst_out_n ks8721cl rst d1, d2: 1n4148 figure 11. recommended reset circuit. vcc r 10k c 10f d1 ks8721cl rst d1: 1n4148 figure 12. recommended circuit for interfacing with cpu/fpga reset at power-on-reset, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the reset out from cpu/fpga provides warm reset after power up. it is also recommended to power up the vdd core voltage earlier than vddio voltage. at worst case, the both vdd core and vddio voltages should come up at the same time. reference circuit for strapping option configuration figure 10 shows the reference circuit for strapping option pins.
april 2005 31 m9999-041405 ks8721cl micrel, inc. ks8721cl led pin 3.3v reference circuits for unmanaged programming through led ports ks8721cl led pin 3.3v pull-up pull-down 220 ? 220 ? 1k ? 10k ? figure 13. reference circuit, strapping option pins
ks8721cl micrel, inc. m9999-041405 32 april 2005 single port number magnetic manufacturer part number auto-mdi-x of ports pulse h1102 yes 1 bel fuse s558-5999-u7 yes 1 ycl ph163112 yes 1 transpower hb726 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 intergrated transformers pulse j0011d21 yes 1 pulse j00-0061 yes 1 table 8. qualified transformer list selection of isolation transformer (1) one simple 1:1 isolation transformer is needed at the line interface. an isolation transformer with integrated common-mode choke is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. characteristic value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma leakage inductance (max.) 0.4 h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms note: 1. the ieee 802.3u standard for 100base-tx assumes a transformer loss of 0.5db. for the transmit line transformer, insertion los s of up to 1.3db can be compensated or by increasing the line drive current by means of reducing the iset resistor value. please select the transfor mer that supports auto-mdi/mdi-x. selection of reference crystal an oscillator or crystal with the following typical characteristics is recommended. characteristic value units frequency 25.00000 mhz frequency tolerance (max.) 100 ppm load capacitance (max.) 20 pf series resistance (max.) 40 ?
april 2005 33 m9999-041405 ks8721cl micrel, inc. package information 48-pin lqfp (lq) micrel inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com this information furnished by micrel in this data sheet is believed to be accurate and reliable. however no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser a grees to fully indemnify micrel for any damages resulting from such use or sale. ? 2004 micrel, incorporated.

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